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Coroutine Co-simulation Test Bench

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cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

v0.4 Release now available source


VHDL and Verilog are both unsuitable for writing complex testbenches. eRM, SystemVerilog and the various SV based methodologies have emerged to address this deficiency. These verification methodologies are large and cumbersome, requiring specialist knowledge, significant time investment and expensive toolchains to achieve satisfactory verification. The overhead of setting up testbenches is onerous so often designers write small throwaway testbenches at a block level and defer the majority of verification to a large system level testbench.

Cocotb intends to bridge this gap in order to make block-level testing useful, reusable, fast, accessible to a much wider skill-set. The net effect is that bugs will be discovered earlier in the design cycle which equates to significant time and cost saving.

Cocotb is ideally suited to FPGA development but also scales to ASIC environments. A testbench can be as simple as basic directed tests through to a complex constrained random verification environment similar to UVM but with the productivity benefit of a higher-level language.

Cocotb is complete open-source, licensed under BSD license and compatible with the Icarus Verilog simulator.

Why verify in Python?

For further details refer to the documentation.

NMI Slidedeck

Slides from the Potential Ventures presentation at the NMI FPGA Verification event:

Similar projects

MyHDL seeks to displace VHDL and Verilog with a Python framework that can generate synthesiable RTL.

Several examples exist of projects providing a VPI interface into a language other than C:

Cocotb tries to build on the advances made by these projects while learning from the direction of UVM and other verification standards.